library ieee;
use ieee.std_logic_1164.all;

entity Counter4_tb is
end entity Counter4_tb;

architecture RTL of Counter4_tb is
	
	component Counter4
	
	port (
		clk, hold_al, clr_al : in bit;
		overFlow : out bit;
		count : out bit_vector(4 downto 0)
	);
	
	end component;
	
	for all : Counter4 use entity work.Counter4(dataflow);
	
	signal clk : bit := '0';
	signal clr_al : bit := '1';
	signal hold_al : bit := '1';
	signal overFlow : bit;
	signal count : bit_vector(4 downto 0);
	
begin
    
	C1 : Counter4 port map(clk, hold_al, clr_al, overFlow, count);
	
	hold_al <= '0' after 1 us, '1' after 2 us;
	clr_al <= '0' after 5 us, '1' after 6 us;

	clk <= not clk after 20 ns;

end architecture RTL;
